JPH048948B2 - - Google Patents
Info
- Publication number
- JPH048948B2 JPH048948B2 JP1261270A JP26127089A JPH048948B2 JP H048948 B2 JPH048948 B2 JP H048948B2 JP 1261270 A JP1261270 A JP 1261270A JP 26127089 A JP26127089 A JP 26127089A JP H048948 B2 JPH048948 B2 JP H048948B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- semiconductor device
- logic circuit
- circuit section
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000872 buffer Substances 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 18
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1261270A JPH02138758A (ja) | 1989-10-07 | 1989-10-07 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1261270A JPH02138758A (ja) | 1989-10-07 | 1989-10-07 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56132066A Division JPS5833864A (ja) | 1981-08-25 | 1981-08-25 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02138758A JPH02138758A (ja) | 1990-05-28 |
JPH048948B2 true JPH048948B2 (en]) | 1992-02-18 |
Family
ID=17359494
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1261270A Granted JPH02138758A (ja) | 1989-10-07 | 1989-10-07 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02138758A (en]) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6342165B2 (ja) * | 2014-01-24 | 2018-06-13 | ルネサスエレクトロニクス株式会社 | 半導体装置及びioセル |
-
1989
- 1989-10-07 JP JP1261270A patent/JPH02138758A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH02138758A (ja) | 1990-05-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2668981B2 (ja) | 半導体集積回路 | |
JPH02177345A (ja) | 半導体集積回路装置 | |
JPS63293966A (ja) | 半導体集積回路装置 | |
JPH0480538B2 (en]) | ||
JPH02219254A (ja) | 半導体集積回路装置 | |
JP3834282B2 (ja) | メモリマクロおよび半導体集積回路 | |
JP3289999B2 (ja) | 半導体集積回路 | |
JPH0221145B2 (en]) | ||
JPH048948B2 (en]) | ||
JPS6070742A (ja) | マスタ・スライス型半導体装置 | |
JPS61208237A (ja) | マスタスライス集積回路 | |
JPH0435065A (ja) | マスタスライス半導体集積回路装置 | |
JPS623584B2 (en]) | ||
JPH06101521B2 (ja) | 半導体集積回路装置 | |
JPH01152642A (ja) | 半導体集積回路 | |
JPS61225845A (ja) | 半導体装置 | |
JPH03203363A (ja) | 半導体装置 | |
JPS61199647A (ja) | 半導体集積回路装置 | |
JP2652948B2 (ja) | 半導体集積回路 | |
JPH0485942A (ja) | 半導体集積回路 | |
JPS60175438A (ja) | 半導体集積回路装置 | |
JP2555774B2 (ja) | 半導体集積回路 | |
JPS63273332A (ja) | 半導体集積回路装置の製造方法 | |
JP2901313B2 (ja) | 大規模集積回路装置 | |
JPS6248042A (ja) | マスタ−スライス方式半導体集積回路 |